3D Packaging & Through-Silicon-Via (TSV)

3D Packaging & Through-Silicon-Via (TSV)

  • ASTRI’s 3D packaging platform has established a full set of 3D packaging solutions, including package design (e.g., PoP, TSV, etc.), process modeling and optimisation (e.g., via formation, via filling, etc.) and performance characterization for different electronics product applications (e.g., memory, CIS, etc.).

    Software for 3D Interconnect Fabrication

    3D-IC is expected to be widely applied in many electronics components, e.g., memory, CMOS image sensor (CIS), radio frequency integrated circuits (RFIC), micro-electro-mechanical-system (MEMS), etc. Copper electroplating, as the major process of 3D interconnect fabrication, is influenced by many parameters including geometry, electrochemistry and physics, therefore, it is very time-consuming and expensive for the industry to use the trial-and-error method to determine the optimal process recipe window.

    ASTRI has developed a software for modeling and simulation of the copper electroplating process to determine the optimal process window for 3D interconnect fabrication, and further shorten the time-to-market of 3D-IC based electronics products. The software, embedding validated numerical models and including four key modules (i.e. user interface, computational engine, optimal process window and result visualization), is able to achieve higher than 90% accuracy of process optimisation window.

    Features

    • Computational engine for via- & wafer-level simulation and copper electroplating process optimization
    • 2D and 3D simulation result visualization

    Applications

    • On-line or off-line simulator of copper electroplating process optimization for TSV manufacturers
    • On-line predictor of optimal process windows for electroplating equipment vendors
    • Off-line simulator for new additive development for TSV electroplating material suppliers
    ASTRI’s software user interface, including wafer pattern input (upper left), 3D simulation result visualization (upper right), key factor analysis (bottom left), and optimal process window (bottom right)
    ASTRI’s software user interface, including wafer pattern input (upper left), 3D simulation result visualization (upper right), key factor analysis (bottom left), and optimal process window (bottom right)

    TSV CMOS Image Sensor Wafer Level Packaging 

    The polymer isolation-based TSV CMOS image sensor is the first low-cost image sensor for TSV which is used successfully for 0.3MP and 5MP with yield more than 95%. It takes advantage of low temperature deposited polymer isolation layer such that the production yield is significantly improved without scarifying its performance while comparing with other CIS packaging techniques.

    Features

    • Low cost and mature production process
    • Low thermal budget technology for the TSV isolation layer – Room temperature chemical vapor deposition (CVD) polymer isolation
    • Specialised wafer level packaging design for hermetic or near hermetic performance
    • Capable for most industrial reliability standards
    • SMT compatible

    Applications

    • Mobile electronics
    • Wireless IC applications such as memory and processor in handheld device

    ec-pack-4