Grafted Polymer Insulator for Through-Silicon-Via (GPI-TSV) Applications (ARD/169)

Through silicon vias (TSVs) are vertical electrical interconnects through thinned silicon dies. Because TSVs greatly reduce interconnect length, TSV-enabled 3D IC packaging can reduce form factor, lower power consumption, and improves heterogeneous integration and electrical performance. TSVs are thus increasingly adopted for many applications such as CIS, MEMS, NAND, and DRAM. However, TSV productions are still costly. For example, conventional SiO2 insulation layers of TSV are fabricated through multiple processes at elevated temperatures with expensive equipment. Alternative is the low-cost polymer TSV insulation; however, most of polymer TSV insulation suffer from Si/polymer interfacial delamination due to weak physical bonding. To address this key issue, we propose grafted polymer TSV insulation (GPI-TSV) technique with novel initiator formulation to enable interfacial chemical bonding stronger than physical bonding. The GPI-TSV technique targets to the market of TSV related products. Based on Yole market reports, the market size has grown quickly and is forecasted to exceed US$14 billion by 2019. The project aims to graft polymers on Si substrates with bonding strength larger than 3.0 N/mm. The project output can benefit material suppliers by licensing initiator and grafting process recipe and TSV manufacturers (especially Hong Kong local companies) with the leverage of material suppliers.