Analog-to-digital converter (ADC) chips, which connect natural signals with digital systems, play a crucial role in various military and civilian applications such as phased-array radar, aerospace, 5G/6G base stations and terminals, automotive, etc. However, U.S. companies hold over 93% of ADC chip market share while China faces restrictions on importing high-end ADC chips due to the Wassenaar Arrangement. Therefore, the development of high-end ADC chips is imperative and aligned with national strategic objectives. This project aims to develop the architecture and circuit design of high-speed and high-resolution ADC for 5G-A/6G terminals in state-of-the-art 22 nm fully-depleted silicon-on-insulator (FD-SOI) technology. A novel hybrid SAR-Flash-SAR ADC architecture with the invention of a 1.5-bit SAR ADC will be adopted to increase ADC performance while maintaining low power consumption. Moreover, a brand-new hybrid architecture combining 2-way interleaved frontend SAR and 4-way interleaved backend SAR will be constructed for performance and cost optimization. This seed project will provide high-end ADC designs for 5G-A/6G terminals and lay a solid foundation for the pipelined platform project of silicon-proven ADC for massive production. It will also pioneer the development of high-end ADC chips in Hong Kong and Mainland China, facilitating the transition from Western-made technologies to domestic alternatives.
