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Feasibility study of a DDR4 analog PHY’s architectural design with industry standard DFI bus interface

Project Title:
Feasibility study of a DDR4 analog PHY’s architectural design with industry standard DFI bus interface
Project Reference:
ARD/120
Project Type:
Seed
Project Period:
20 / 02 / 2013 - 19 / 08 / 2013
Funds Approved (HK$’000):
1980
Project Coordinator:
Mr David Kwong
Deputy Project Coordinator:
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Deliverable:
Research Group:

Dr K C Wang
Mr Simon Lee
Mr Andy Wu
Ms Jennifer Ho
Mr Ka Hung Kwok
Mr K C Au
Mr K C Wan
Ms Sidar Lai


Sponsor:
Description:
Co-Applicant:
/
Keywords:
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