There are growing market interests for new features such as supporting high-dimension MIMO to increase the spectral efficiency in 5G and beyond systems. In general, the higher the MIMO dimension, the higher the spectral efficiency, but at the same time the higher the receiver complexity. Hence it is imperative to balance the performance and complexity of the MIMO receiver. On the other hand, owing to their advantages such as supply chain diversity, cost competitiveness and design flexibility, the next generation chipset platforms (e.g. RISC-V CPU+FPGA/GPU) are gaining a lot of traction and emerging as viable alternatives to the mainstream chipset platforms. In order to address these market needs, and as part of the continuous effort to extend ASTRI’s 5G technology portfolio, the project team will: a) Design a reduced-complexity receiver for supporting high-dimension MIMO b) Study on the architecture design and profiling for 5G base station using the next generation chipset platforms The outcome of this project enables ASTRI to engage the industry to develop 5G base station reference design with new features and pre-6G PoC systems in follow-on platform project(s). = Notes = MIMO: Multiple Input Multiple Output CPU: Central Processing Unit GPU: Graphics Processing Unit FPGA: Field Programmable Gate Array RISC-V: Fifth Version of Reduced Instruction Set Computing Architecture PoC: Proof of Concept
