Dr Beiping YAN
Dr Xiaowu CAI
As CMOS technology is scaling below 20nm, traditional planar devices cannot meet requirements for scalability and leakage due to their poor gate controllability over the channel. FinFET (Fin Field Effect Transistor) technology has emerged as a new generation CMOS technology. Compared with traditional planar MOS transistor, FinFET technology can provide enhanced gate control and lower leakage current with its 3D channel structures. Meanwhile, FinFET structures also raise several design challenges in ESD (Electrostatic Discharge) design. One challenge is generally related to the scaling process. ESD design window will shrink with reduced oxide breakdown voltage. And due to the 3D thin fin structure, thermal conduction and discharge will be very difficult. ESD protection effect will be greatly affected in traditional Gate-Grounded NMOS (GGNMOS) and diode. Moreover, the effective ESD path will be reduced due to the design rules of FinFET process. This project focuses on ESD simulation-design methodology. By using TCAD (Technology Computer Aided Design) simulation, TLP(Transmission Line Pulse) curves and ESD capability of FinFET structure will be explored, and the inside relationship of ESD capability and design parameters will be established.
