With the progress in wireless communication and network technology, the working frequency and data transmission rate of the system have increased to GHz and Gbit. Meantime, the reliability concern has made ESD/surge protection become an important issue. For RF circuit interfaces, problems of ESD-to-Circuit interactions have emerged as a major challenge. This project not only targets at developing on-chip low-capacitance (low-c) ESD structure for RF circuit ESD protection, but also target at developing on-board low-c structure for ESD/surge protection for high speed data lines. The virtual fab approach is presented as the basis of a complete ESD design methodology. The methodology will employ Synopsys TCAD as simulation tool. By process design and device parameter optimization, the low-c ESD structure can be conceived and optimized at the pre-silicon phase. ESD structure and related IO cells will be verified in specified process nodes. And customized low-capacitance IO Cells can be generated for on-chip ESD protection or on-board high speed ESD/surge protection. This project is reliability research of electronic products, which is not only provide chip level ESD protection, but also provide system level ESD/surge protection solutions. The successfully implementation will make our electronic products such as mobile phone, PC etc. more reliable and safer.
Low Capacitance ESD Structures for RF Applications (ART/221CP)
21 / 02 / 2017 - 20 / 02 / 2019
Dr Beiping YAN