Dual Mode Digital TV Receiver Chip and Reference Design
ART/066CP
20090625 - 20110324
14788
Dr Danny Chung-yen Ong
The project deliverables are listed in the following.
i. Dual Mode DTMB Baseband System Design
. Dual Mode DTMB system specification
. Architecture design and hardware sharing for multi-carrier and single carrier systems
. Dual Mode System algorithm development and simulation, including single carrier synchronization, channel estimation and equalization.
Both floating point and fixed point simulation for dual mode DTMB are to be developed to verify the functionalities and measure the performance. Pertinent simulation platform, including test benches and test vectors generation, supports hardware implementation.
ii. Dual Mode DTMB Baseband FPGA Design and Testing
. FPGA architecture design
. FPGa Module Design and Implementation, including single carrier synchronization, channel estimation and equalization etc.
. Dual Mode baseband FPGA integration
iii. Dual Mode DTMB Hardware Board Design
. FPGA demo board design, PCB layout, and integration. The board will be integrated and tested to demonstrate Dual Mode DTMB functionality and performance. Integration with RF tuner is optional at this stage.
. FPGA based system verification and testing
iv. DTMB Baseband ASIC Design
. ASIC chip design specification
. ASIC chip architecture design
- Baseband architecture design includes architecture design in ASIC chip, as well as baseband board levels. Such architecture design takes overall design objectives (low power, low cost, high efficiency and good performance, etc.) into account and optimize hardware resources and performance tradeoff in the architecture level.
. Front-End ASIC Design and Implementation, including FPGA to ASIC porting, RTL synthesis and Formal verification
. Back-End Design and Implementation
. Dual Mode Chip Tape Out
v. IP Development and Patent Applications
. At least two patents in the Dual Mode DTMB system and implementation will be generated in the project.
vi. Industry contribution and sponsorship
We will actively seek for customers and partners and industry contribution for at least 10% of total budget in the entire project and continue after the end of project. The goal is to promote the technology and project deliverables and gain industry contribution for the project.
Cadence [Sponsor]
This project aims to develop a Digital TV receiver core, IPs, and ASIC design with both single carrier and multi-carrier functionalities for China terrestrial and mobile digital TV applications, specifically the China compulsory Digital terrestrial TV standard, DTMB. This project is a natural continuation of ITF project, “OFDM Core for Digital TV Applications”. While the previous project developed an OFDM core and ASIC design especially for the DTMB multi-carrier mode, this project aims to develop a dual mode DTMB chip which will be fully compliant with the DTMB standard, upon the technology being developed. In addition, reference design will be provided for this chip as well. The transition from analog TV to digital TV presents tremendous market opportunities as well as technology innovation. Numerous applications have been identified for digital TV technologies, far beyond the traditional analog TV. Especially in China, with the national standard DTMB being deployed in the next three to five years, the technology revolution will certainly generate significant market momentum with tremendous market opportunities, given that there exist more than 380 million TV sets in China and the DTV technologies can be installed or equipped in many other devices. This project is at the right market window and follows technology trend. Product and application driven R&D methodology will be adopted to accomplish the project objective. The IPs and technology developed will enable DTV industry in Hong Kong, PRD, and China to benefit from the significant technology transition and enormous market opportunities. The project team will actively engage customers and partners from the early stage of project so they can benefit from the ASTRI’s technologies and IPs.