Advanced Ceramic Substrate for High Power & High Frequency Applications (ACS) (ART/244CP)

Advanced Ceramic Substrate for High Power & High Frequency Applications (ACS) (ART/244CP)

  • Advanced Ceramic Substrate for High Power & High Frequency Applications (ACS) (ART/244CP)
    01 / 01 / 2018 - 31 / 12 / 2019

    Dr Daniel Xunqing SHI

    1. Establishment of experimental platform for formulation, synthesis, & performance evaluation of butterfly-mode plating (BMP) recipes. 2. Design of substrates with feature pattern including RDL trace/Cu pillar (20um-50um) and through-hole (50um-150um) and fabrication of the designed substrate samples (500 pieces). 3. Investigate the BMP process and material formulae for through-hole filling applications, including the Reverse Periodic Pulse (RPP) and Additional Differential Etching (ADE) process parameter optimization, formula design of accelerator & inhibitor, formula design of etching catalyst & stabilizer, characterization and performance evaluation of the material formulae to achieve TP>200%. 4. Investigate the RPP process and material formulae for RDL trace/Cu pillar electrodeposition applications, including process parameter optimization, leveler formula design and characterization, and performance evaluation to achieve trace/pillar surface flatness <=5% and panel-level uniformity >=90% . 5. Finalize the material recipe and process parameters with the concrete performance evaluation, reliability testing, field testing data for the fabrication of the designed substrates with RDL trace/Cu pillar of 20um-50um & through-holes with diameter of 50um-250um and thickness of 200um~500um. 6. Contract Service Deliverables for Customer 1 Design of Experiment (DOE) for the processes that are related to the interfacial voids at Cu-Filled blind vias, substrate samples fabrication, report on reliability test and analysis. 7. Contract Service Deliverables for Customer 2 -Design report on high power substrate (including RDL & Cu-pillar Bumps, power module, passive devices, heat sink, driver board and its power supply) including design, simulation and manufacturing process flow; prototype samples (5 sets of prototype samples & 5 sets of final prototype samples); performance testing report and technology transfer. -Design report on thermal sensor monitoring for high power substrate (including RDL & Cu-pillar Bumps) and 50 sets of thermal sensor prototype samples. 8. Contract Service Deliverables for Customer 3 Report on copper via filling process design and on-site evaluation of plating solution; Recipe report on copper via filling additives of accelerator, suppressor and leveler including raw materials, formulation and production process for advanced substrate application; 1000 liter via filling additive and 1000 liter flash etching additive with ASTRI’s material recipe for field tests and evaluation. 9. Contract Service Deliverables for Customer 4 Report on plating performance evaluation of screened material recipes for rigid substrate application; 1000 litre via filling additive with ASTRI's material recipe for field tests.

    Huawei Technologies Co., Ltd.
    Oriental Source (H.K.) Co., Limited
    Supergold Technology (Hong Kong) Company Ltd.

    The demand for fine line/space pattern formation and high power application of advanced ceramic substrates has promoted the development of DPC (Direct Plated Copper) ceramic substrate technology. Compared with LTCC, HTCC, and DBC (Direct Bonded Copper) ceramic substrates, DPC substrate also has the advantages of surface flatness and smaller trace alignment error. The DPC technology continues to advance for higher power, microwave application, and lower cost by changing the Ag plugged hole process to the Cu filled hole process. Due to the size and aspect ratio characteristic of through holes in DPC ceramic substrates, completely filling the through holes along with the surface circuitry formulation are extremely challenging. This full project proposes our solutions by developing the fabrication process and materials of DPC substrate to conquer the challenges of void-free through-hole filling, meanwhile meet the requirement of surface plated thickness, and surface flatness for circuitry formulation. A butterfly-mode plating process is employed for through hole filling by optimizing pulse plating waveform, organic additives, and agitation condition in the hole. In addition, a differential etching process is added to enhance the butterfly-mode plating and control the surface plated thickness. A novel molecule structure is designed for the plating levelers in order to achieve the requirement of surface flatness and panel level uniformity of copper plated trace and bumps.