Home > Second Generation Double-Data-Rate (DDR2) Digital Controller and PHY Second Generation Double-Data-Rate (DDR2) Digital Controller and PHY Project Title:Second Generation Double-Data-Rate (DDR2) Digital Controller and PHY Project Reference:ARD/045 Project Type: Project Period:20081231 - 20090630 Funds Approved (HK$’000):1960 Project Coordinator:Dr Shen-chang Chao Deputy Project Coordinator: Deliverable: Research Group: Sponsor: Description: Co-Applicant: Keywords:
