Home > Second Generation Double-Data-Rate (DDR2) Digital Controller and PHYSecond Generation Double-Data-Rate (DDR2) Digital Controller and PHYProject TitleSecond Generation Double-Data-Rate (DDR2) Digital Controller and PHYProject ReferenceARD/045Project TypeProject Period20081231 - 20090630Funds Approved (HK$’000)1960Project CoordinatorDr Shen-chang ChaoDeputy Project CoordinatorDeliverableResearch GroupSponsorDescriptionCo-Applicant
