Suzhou Vega Technology Co., Ltd
Diresense (Hong Kong) Co., Limited
PHOTOOL INTERNATIONAL CO., LIMITED
Supergold Enterprise International Limited (CS)
With Moore's Law approaching its limit and the foundry's process approaching its physical limit, foundries have begun to deploy advanced packaging technologies to ensure future competitive positions. Advanced packaging is an inevitable choice in the post-Moore era, including flip-chip, wafer-level packaging, fan-in and fan-out, 3D IC, and system-in-package (SiP) packaging. Advanced packaging is redefining the status of packaging in the semiconductor industry chain, and the impact of packaging on chip performance is further improving. At present, the market size of advanced packaging has been occupied for almost half of the entire semiconductor industry. Since there is a dramatically increasing demand of advanced mid-end wafer packaging processes such as the wafer bump, redistribution layer (RDL), and through silicon via (TSV), and the technical barriers are also increased dramatically. This is mainly manifested in that the critical dimensions of wafer bump, RDL, and TSV are getting smaller and smaller. After entering 2020s, the minimum size of the key packaging processes goes to less than 5 μm, and the packaging processes are basically stacked and going to spatial three-dimensional. Its complexity is more like to build a complicate house inside a chip. Therefore, more and more stringent requirements are put forward for the in-line inspection which need to combined both 2D and 3D. The accuracy of all inspection methods must be reached to the sub-micron level, meanwhile taking into account the limited inspection speed, inspection of TSV with high aspect ratio, and the bump defect inspection with optical shadow problem, giving rise to the technology pain points encountered by the industry at present. Thus, the 3D precision metrology technology that is fast, accurate, with no shadow effect, and capable of deep hole inspection is becoming important due to the emerging demand of advanced mid-end semiconductor packaging processes. The proposed high speed coaxial confocal line scanning technology can cover almost the whole range of the mid-end semiconductor packaging process. In this project, 3D precision metrology solution for wafer bumps, RDLs, and TSVs with dimensions less than 5 μm will be a breakthrough. This project will use the short blue-green wavelength range to be the measurement wavelength, and the diffraction limitation of the optical system reaches 0.5 μm. The design of the coaxial telecentric optical path enables the system to measure the TSV with aspect ratio reaching 8 or above. The implementation of hardware acceleration embedded system can make the line scanning speed reach 4000 lines/sec or above. In terms of software, multi-layer algorithm and wavelet transform algorithm will be developed to solve the problem of multi-layer interface reflection in transparent object. So that the 3D point clouds of each layer can be clearly obtained.