AppoTech Limited
The global chip market is growing rapidly. While Artificial Intelligence Generated Content (AIGC) technology has shown rapid progress recently, its application in chip digital logic design remains limited. This project aims to perform R&D in utilizing AIGC technology to provide AI-assistance in digital logic design to speed up the process and to reduce the development cost. The project will train AIGC Domain Specific Language Model (DSLM) to understand digital logic design methodology and to generate digital logic design codes. It will implement various types of training data to train the DSLM to understand digital logic design using the Chain-of-Thought (CoT) methodology. The training data includes Prompt-Guided data and Code-Comment Alignment data. The project will also apply CoT with Reflexion prompt engineering technology to guide the system to generate the requested digital logic design code. This AI technology can be extended to other verification stages of chip industry to accelerate chip design process and the chip products entry to the market. This project aims to train the digital design system to be capable of designing the fundamental digital logic components in chip design, and to serve as an exploration of AI-assisted chip design methodology for further application in more complex design.
