Job Description
CTO/ICS/MLP/2993a-b
2
The Hong Kong Applied Science and Technology Research Institute (ASTRI) was founded by the Government of the Hong Kong Special Administrative Region in 2000 with the mission of enhancing Hong Kong’s competitiveness through applied research. ASTRI’s core R&D competence in various areas is grouped under four Technology Divisions: Communications Technologies, Trust and AI Technologies, Integrated Circuits and Systems, and IoT Sensing and AI Technologies.
It is applied across six core areas which are Smart City, Financial Technologies, Intelligent Manufacturing and Re-Industrialization, Digital Health, Application Specific Integrated Circuits, and Metaverse.
Over the years, ASTRI has nurtured a pool of research, I&T talents and received numerous international awards for its pioneering innovations as well as outstanding business and community contributions. To date, ASTRI has transferred over 800 technologies to the industries and been granted more than 900 patents in the Mainland, the US, and other countries.
It is applied across six core areas which are Smart City, Financial Technologies, Intelligent Manufacturing and Re-Industrialization, Digital Health, Application Specific Integrated Circuits, and Metaverse.
Over the years, ASTRI has nurtured a pool of research, I&T talents and received numerous international awards for its pioneering innovations as well as outstanding business and community contributions. To date, ASTRI has transferred over 800 technologies to the industries and been granted more than 900 patents in the Mainland, the US, and other countries.
Job Responsibilities
- Deep learning related FPGA/ASIC/SoC hardware design, development and evaluation
- Work with software and algorithm team to come up with an optimized hardware architecture
- Participating in system design, implementation, and optimization for commercialization
- Assist in R&D project’s planning and management
- Lives ASTRI values
Requirements
- PhD holder or Master’s degree in Computer Engineering, Electronic Engineering, Information Engineering, IC Design or relevant disciplines with minimum 3 years of related experience. Candidates with less experience may also be considered.
- Experience in Verilog RTL coding, testbench design, FPGA prototyping and verification is highly preferred.
- Experience in ASIC/FPGA build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure is an advantage
Application
Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.
Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email (preferable) or post no later than :
Email: [email protected]
Post: 5/F, Photonics Centre, 2 Science Park East Avenue,
Hong Kong Science Park, Shatin, Hong Kong.
Only short-listed candidates will be notified. Personal data provided by applicants will be used for recruitment purposes only.