纳米系统级芯片设计技术
ART/060CP
20090504 - 20110228
13197
李耀基先生
There are total five 65nm Silicon IP’s will be developed in this project.
Commonly needed Silicon IP’s in 65nm
1. Low Voltage Pipelined ADC
2. Low Voltage Audio Codec
3. Low Power Highly Programmable Digital PLL
Yield Enhancement Silicon IP’s in 65nm
4. Dynamic Process Variation Scaling
5. Adaptive Clock Tree Synchronizer
The following items will be included in the final IP package for each of the above IP’s:
a. Silicon IP prototype for evaluation
b. Physical layout in GDSII format
c. Timing data in SDF format
d. Parasitic data in SPEF format
e. Post layout netlist in Verilog format
f. Verification Model for DRC/LVS
g. Timing Model for functional simulation
h. EDA Model for Formal Verification
i. Timing Model for Static Timing Analysis
j. Integration guideline for Design For Test
k. Simulation vectors for Design For Test
l. Place and Route Model for physical design
卓荣集成电路科技
明导(上海)电子科技有限公司 [赞助机构]
深圳市芯华集成电路科技有限公司
由於集成电路複杂程度的大幅增加和低成本的要求，硅工艺越来越朝更小的尺寸发展。为提高本地集成电路业界的竞争力，我们将开发一个系统纳米级芯片的设计平台。此设计平台将需要系统级纳米芯片的专业技术，这些技术通常包括软IP和硬IP。在本申请的项目中一些低电压的硬IP将被开发出来。单一的电源供电将打破需要提供更高电压接口的限制。此外用於高速系统级芯片和IO接口电路的高性能的锁相环电路（PLL）将被开发出来。