納米系統級芯片設計技術
ART/060CP
20090504 - 20110228
13197
李耀基先生
There are total five 65nm Silicon IP’s will be developed in this project.
Commonly needed Silicon IP’s in 65nm
1. Low Voltage Pipelined ADC
2. Low Voltage Audio Codec
3. Low Power Highly Programmable Digital PLL
Yield Enhancement Silicon IP’s in 65nm
4. Dynamic Process Variation Scaling
5. Adaptive Clock Tree Synchronizer
The following items will be included in the final IP package for each of the above IP’s:
a. Silicon IP prototype for evaluation
b. Physical layout in GDSII format
c. Timing data in SDF format
d. Parasitic data in SPEF format
e. Post layout netlist in Verilog format
f. Verification Model for DRC/LVS
g. Timing Model for functional simulation
h. EDA Model for Formal Verification
i. Timing Model for Static Timing Analysis
j. Integration guideline for Design For Test
k. Simulation vectors for Design For Test
l. Place and Route Model for physical design
卓榮集成電路科技
明導(上海)電子科技有限公司 [贊助機構]
深圳市芯華集成電路科技有限公司
由於集成電路複雜程度的大幅增加和低成本的要求，硅工藝越來越朝更小的尺寸發展。為提高本地集成電路業界的競爭力，我們將開發一個系統納米級芯片的設計平台。此設計平台將需要系統級納米芯片的專業技術，這些技術通常包括軟IP和硬IP。在本申請的項目中一些低電壓的硬IP將被開發出來。單一的電源供電將打破需要提供更高電壓接口的限制。此外用於高速系統級芯片和IO接口電路的高性能的鎖相環電路（PLL）將被開發出來。