Nanometer SoC Design Technology (NSDT)
20090504 - 20110228
Mr Yiu-kei Li
There are total five 65nm Silicon IP’s will be developed in this project. Commonly needed Silicon IP’s in 65nm 1. Low Voltage Pipelined ADC 2. Low Voltage Audio Codec 3. Low Power Highly Programmable Digital PLL Yield Enhancement Silicon IP’s in 65nm 4. Dynamic Process Variation Scaling 5. Adaptive Clock Tree Synchronizer The following items will be included in the final IP package for each of the above IP’s: a. Silicon IP prototype for evaluation b. Physical layout in GDSII format c. Timing data in SDF format d. Parasitic data in SPEF format e. Post layout netlist in Verilog format f. Verification Model for DRC/LVS g. Timing Model for functional simulation h. EDA Model for Formal Verification i. Timing Model for Static Timing Analysis j. Integration guideline for Design For Test k. Simulation vectors for Design For Test l. Place and Route Model for physical design
AppoTech Limited Mentor Graphics Corporation [Sponsor] ShenZhen XinHua Integrated Circuit Tech. Co. Ltd.
Silicon processes have been migrating to finer geometries due to the higher IC complexity demands and lower cost requirements. A Nanometer System-On-Chip Design Platform will improve competitiveness of local IC industry. The design platform should include nanometer SoC design knowhow, commonly needed soft and silicon IP’s. In this proposed project, a few low voltage silicon IP’s will be developed. The single power supply will break the scaling barrier of maintaining a higher voltage interface. In addition, high performance PLL will be developed for high speed SoC and IO interface designs.