光纤通讯适用的高速集成电路
ART/108CP
20101115 - 20130314
17453
王克中博士
The deliverables of the proposed projects are listed below: 1. System architecture, core IPs, test circuits, test data, and initial qualification results of transceiver ICs and dual-channel IC arrays for Light Peak, Ethernet, or other optical communication applications. - 65nm CMOS transceiver IC with laser driver, TIA and other blocks of a transceiver for 10Gb/s application - 0.13um SiGe BiCMOS transceiver IC with laser driver, TIA and other building blocks of a transceiver for 25Gb/s application 2. High-speed packaging and testing procedures for the above test circuits 3. A system architecture design for optical coherent transmission and best-effort key IP blocks suitable for supporting 40 and 100 Gb/s optical coherent receivers. – Designs, simulations, layout, and simulation data of 40nm CMOS key IP blocks of the 8-bit 56 Giga-Sample per second (GS/s) ADC and 14 GHz 100fs-jitter(rms) PLL.
国际商业机器中国香港有限公司 [赞助机构]
Sana Seminconductor [赞助机构]
在所有通讯技术中， 光纤通讯可提供最高的传输数据率 (每只光纤每秒10万亿位元以上) 以及最长的距离 (超过1万公里)。 每秒100亿位元或更高数率的高速集成电路是促成此类光纤通讯的主要元件。在中国及世界其他地区，光纤通讯市场正在快速成长。可是在本港这种高速集成电路的研发很少。我们提议在香港开发这类的高速集成电路，应用到每秒100，400，以及100亿位元的光纤通讯市场。我们希望以这个方案的成果作为香港未来超高速集成电路研发的基础。