High Speed Integrated Circuits for Optical Fiber Communication (ICOFC)
20101115 - 20130314
Dr Keh-chung Wang
The deliverables of the proposed projects are listed below: 1. System architecture, core IPs, test circuits, test data, and initial qualification results of transceiver ICs and dual-channel IC arrays for Light Peak, Ethernet, or other optical communication applications. - 65nm CMOS transceiver IC with laser driver, TIA and other blocks of a transceiver for 10Gb/s application - 0.13um SiGe BiCMOS transceiver IC with laser driver, TIA and other building blocks of a transceiver for 25Gb/s application 2. High-speed packaging and testing procedures for the above test circuits 3. A system architecture design for optical coherent transmission and best-effort key IP blocks suitable for supporting 40 and 100 Gb/s optical coherent receivers. – Designs, simulations, layout, and simulation data of 40nm CMOS key IP blocks of the 8-bit 56 Giga-Sample per second (GS/s) ADC and 14 GHz 100fs-jitter(rms) PLL.
IBM China/Hong Kong Limited [Sponsor] Sana Seminconductor [Sponsor]
Optical Fiber Communication (OFC) offers the highest date rate (> 10 Tb/s over a single fiber) and the longest distance (> 10,000Km) among all communication technologies. High-speed ICs at data rates 10 Gb/s and higher are key enablers of OFC. There is a potentially large and rapidly growing OFC market in China as well as in the rest of the world. However, there are little local R&D activities to support such IC development. We propose to develop the high-speed ICs for 10, 40, and 100 Gb/s optical fiber communications in Hong Kong to address the optical fiber communication market. We plan to use this project as the R&D foundation for future work in the ultrahigh speed IC area in Hong Kong.