光纖通訊適用的高速集成電路
ART/108CP
20101115 - 20130314
17453
王克中博士
The deliverables of the proposed projects are listed below: 1. System architecture, core IPs, test circuits, test data, and initial qualification results of transceiver ICs and dual-channel IC arrays for Light Peak, Ethernet, or other optical communication applications. - 65nm CMOS transceiver IC with laser driver, TIA and other blocks of a transceiver for 10Gb/s application - 0.13um SiGe BiCMOS transceiver IC with laser driver, TIA and other building blocks of a transceiver for 25Gb/s application 2. High-speed packaging and testing procedures for the above test circuits 3. A system architecture design for optical coherent transmission and best-effort key IP blocks suitable for supporting 40 and 100 Gb/s optical coherent receivers. – Designs, simulations, layout, and simulation data of 40nm CMOS key IP blocks of the 8-bit 56 Giga-Sample per second (GS/s) ADC and 14 GHz 100fs-jitter(rms) PLL.
國際商業機器中國香港有限公司 [贊助機構]
Sana Seminconductor [贊助機構]
在所有通訊技術中， 光纖通訊可提供最高的傳輸數據率 (每隻光纖每秒10萬億位元以上) 以及最長的距離 (超過1萬公里)。 每秒100億位元或更高數率的高速集成電路是促成此類光纖通訊的主要元件。在中國及世界其他地區，光纖通訊市場正在快速成長。可是在本港這種高速集成電路的研發很少。我們提議在香港開發這類的高速集成電路，應用到每秒100，400，以及100億位元的光纖通訊市場。我們希望以這個方案的成果作為香港未來超高速集成電路研發的基礎。