先进器件IP 平臺
ART/187CP
20150319 - 20170318
12592
严北平博士
1. Device design and tape out (40 nm) 1a) 40 nm tape out for TLP (Transmission Line Pause) testing structures (several hundred), which are used to optimize and determine the ESD design rule. 1b) 40 nm device design report, which states the ESD design methodology. 1c) 40 nm TLP characterization report, which includes ESD design rules. 2. Analog IO cells design and tape out (40 nm) 2a) 40 nm tape out for analog IO cells 2b) 40 nm design report (IO cells) 2c) 40 nm ESD testing report 3. Device design and tape out (55 nm) 3a) 55 nm tape out for TLP (Transmission Line Pause) testing structures (several hundreds), which are used to optimize and determine the ESD design rule. 3b) 55 nm device design report, which states the ESD design methodology. 3c) 55 nm TLP characterization report, which includes ESD design rules. 4. Analog IO cells design and tape out (55 nm) 4a) 55 nm tape out for analog IO cells 4b) 55 nm design report (IO cells) 4c) 55 nm ESD testing report
霍晓博士
蔡小五博士
陈中子博士
魏晨曦先生
Mdm Angela TONG
Mr Tao SUN
Miss Sidar Lai
Mr Yuan Lei
Mr Yichen Li
任俊傑先生
Mr Michael Kwok Wah Chu
HLMC (特许授权) [赞助机构]
中芯国际（SMIC） [赞助机构]
上海华力微电子公司（HLMC） [赞助机构]
SMIC (特许授权) [赞助机构]
可靠性是纳米技术最为重要的议题之一，尤其是对超薄栅MOS器件。瞬态电压拟制器件（TVS）是达到高可靠性的唯一途径。该项目力图发展新颖的TVS结构，在这些新的TVS结构基础上建立定制的IOESD保护电路单元，并通过多次MPW计划在40/55 纳米CMOS工艺中验證我们的设计。 在此平臺中，将采用虚拟硅工厂技术对不同类型的TVS结构进行设计和优化。传统的GGNMOS/GDPMOS结构也将同时被设计以便与新的结构进行比较。特定工艺的关键ESD实验参数将通过参数化的结构来提取。在新的TVS结构的基础上定制的保护方案可以方便快速地提供。面积有效的TVS结构发展将帮助IC 代工厂和设计公司增强它们产品的竞争力。