先進器件IP 平臺

先進器件IP 平臺

  • 先進器件IP 平臺
    ART/187CP
    20150319 - 20170318
    12592

    嚴北平博士
    1. Device design and tape out (40 nm) 1a) 40 nm tape out for TLP (Transmission Line Pause) testing structures (several hundred), which are used to optimize and determine the ESD design rule. 1b) 40 nm device design report, which states the ESD design methodology. 1c) 40 nm TLP characterization report, which includes ESD design rules. 2. Analog IO cells design and tape out (40 nm) 2a) 40 nm tape out for analog IO cells 2b) 40 nm design report (IO cells) 2c) 40 nm ESD testing report 3. Device design and tape out (55 nm) 3a) 55 nm tape out for TLP (Transmission Line Pause) testing structures (several hundreds), which are used to optimize and determine the ESD design rule. 3b) 55 nm device design report, which states the ESD design methodology. 3c) 55 nm TLP characterization report, which includes ESD design rules. 4. Analog IO cells design and tape out (55 nm) 4a) 55 nm tape out for analog IO cells 4b) 55 nm design report (IO cells) 4c) 55 nm ESD testing report
    霍曉博士 蔡小五博士 陳中子博士 魏晨曦先生 Mdm Angela TONG Mr Tao SUN Miss Sidar Lai Mr Yuan Lei Mr Yichen Li 任俊傑先生 Mr Michael Kwok Wah Chu
    HLMC (特許授權) [贊助機構] 中芯國際(SMIC) [贊助機構] 上海華力微電子公司(HLMC) [贊助機構] SMIC (特許授權) [贊助機構]

    可靠性是納米技術最為重要的議題之一,尤其是對超薄柵MOS器件。瞬態電壓擬制器件(TVS)是達到高可靠性的唯一途徑。該項目力圖發展新穎的TVS結構,在這些新的TVS結構基礎上建立定制的IOESD保護電路單元,并通過多次MPW計劃在40/55 納米CMOS工藝中驗證我們的設計。 在此平臺中,將採用虛擬硅工廠技術對不同類型的TVS結構進行設計和優化。傳統的GGNMOS/GDPMOS結構也將同時被設計以便與新的結構進行比較。特定工藝的關鍵ESD實驗參數將通過參數化的結構來提取。在新的TVS結構的基礎上定制的保護方案可以方便快速地提供。面積有效的TVS結構發展將幫助IC 代工廠和設計公司增強它們產品的競爭力。