Advanced Device IP Platform

Advanced Device IP Platform

  • Advanced Device IP Platform
    ART/187CP
    20150319 - 20170318
    12592

    Dr Beiping Yan
    1. Device design and tape out (40 nm) 1a) 40 nm tape out for TLP (Transmission Line Pause) testing structures (several hundred), which are used to optimize and determine the ESD design rule. 1b) 40 nm device design report, which states the ESD design methodology. 1c) 40 nm TLP characterization report, which includes ESD design rules. 2. Analog IO cells design and tape out (40 nm) 2a) 40 nm tape out for analog IO cells 2b) 40 nm design report (IO cells) 2c) 40 nm ESD testing report 3. Device design and tape out (55 nm) 3a) 55 nm tape out for TLP (Transmission Line Pause) testing structures (several hundreds), which are used to optimize and determine the ESD design rule. 3b) 55 nm device design report, which states the ESD design methodology. 3c) 55 nm TLP characterization report, which includes ESD design rules. 4. Analog IO cells design and tape out (55 nm) 4a) 55 nm tape out for analog IO cells 4b) 55 nm design report (IO cells) 4c) 55 nm ESD testing report
    Dr xiao HUO Dr Xiaowu CAI Dr Zhongzi CHEN Mr Chenxi WEI Mdm Angela TONG Mr Tao SUN Miss Sidar Lai Mr Yuan Lei Mr Yichen Li
    HLMC (licensing) [Sponsor] Semiconductor Manufacturing International Corp. (SMIC) [Sponsor] Shanghai HuaLi Microelectronics Corporation (HLMC) [Sponsor] SMIC (Licensing) [Sponsor]

    Reliability is one of the most important issues for nano-meter (nm) technology, especially for ultra-thin gate MOS devices and transient voltage suppressors (TVS) protection is the only way to reach high reliability. This project targets to develop novel TVS structures, establishing customized IO protection circuit cells based on the TVS structures, and validating them in 40/55 nm CMOS technologies through multiple MPW. Different types of TVS structures will be designed and optimized using virtual fab technologies. Traditional GGNMOS/GDPMOS will also be designed for comparison with the enabling structures. Critical ESD experimental parameters for a given technology node will be extracted through parameterized testing structures. Based on the new TVS structures, a customized protection scheme can be provided easily and rapidly from this platform. The development of the area-efficient TVS structures will help IC foundries and design houses enhance their competitiveness.