無線傳感器網絡信號處理器平台
ART/133CP
20120401 - 20131231
13350
鄺國權先生
1. 0.18um Analog Front End (AFE) IP block consists of a programmable gain amplifier, a bandgap reference, a 12 bit resolutions DAC and a 8-channel 12-bit resolution ADC.
2. A 0.18um wireless sensor signal processing SoC with the Analog Front End together with a ARM Cortex M0 RISC processor.
3. 0.13um Analog Front End (AFE) IP block consists of a programmable gain amplifier, a bandgap reference, a 12 bit resolutions DAC and a 8-channel 14-bit resolution ADC.
4. A 0.13um wireless sensor signal processing SoC with the Analog Front End together with a ARM Cortex M0 RISC processor.
5. PCB demo module of e-health application (based on 0.13um wireless sensor signal processing SoC) to enable licensees to develop WSN products
6. PCB demo module of green energy application (based on 0.13um wireless sensor signal processing SoC) to enable licensees to develop WSN products 7. Full design documentation and application notes for end users.
這個項目提出了一個無線傳感器網絡信號處理器平台處理各種各樣的傳感器電子保健應用程式。該平台包括一個高精度，低功耗模擬前端（AFE）塊，一個能連接到外罝藍牙或ZigBee射頻收發器的高性能數字信號處理器。