Develop and transfer to industry the design technology platform for CCD sensor image signal processing and conditioning which can be used in building integrated image signal processors with on-board timing logic or high voltage CCD clock drivers. The platform specific IPs will include the following key circuit technologies :
1) General purpose digital cells for logic (standard cell and gate array cell) in BiCMOS and CMOS processes. Libraries will consist of common primitives for logic implementation and include schematic, layout and Verilog models for simulations.
2) Analog Image Signal Processing (ISP) building IPs in Mixed Signal BiCMOS process: tape-out test chips to validate the functionalities and performance of these IPs. These circuits will be implemented in both 5V and 3.3V BiCMOS processes.
3) Develop 3.3 V-0.35u CMOS image signal processing AFE (Analog Front End) for colour CCD camera: include CMOS analog ISP building block IPs, high speed data converters ( ADC - Analog to Digital Converter and DAC - Digital to Analog Converter), tape-out and evaluate the AFE module to validate IPs functionalities and performance for commercial applications
MiniLogic Device Corporation
微创高科有限公司 (赞助机构)
本项目将研发专用集成电路设计平臺，主要用於混合信号CCD图像传感处理。该设计平臺以提高性能、降低成本、提升技术和实现商业化为目标，适用於CCD图像传感处理、数据转换、时序产生和CCD高压时鐘驱动等周边集成电路。主要的电路设计包括核心图像信号处理IP、高速低功耗数据转换器（ADC和DAC），标準数字逻辑单元、高精度振荡器以及高电压时鐘驱动器等，其芯片将用BiCMOS或CMOS工艺製成，可用於开发低成本低功耗高集成度的CCD图像信号处理子系统（黑白或彩色）的解决方案。这一项目所开发的技术将不仅增强CCD图像传感处理电路的竞争力，其核心模拟IP还可以应用到CMOS图像传感处理电路中。
