用於 CCD 圖像傳感處理的混合信號專用集成電路設計平臺
ART/010CP
20070103 - 20081102
10840
鄺國權先生
Develop and transfer to industry the design technology platform for CCD sensor image signal processing and conditioning which can be used in building integrated image signal processors with on-board timing logic or high voltage CCD clock drivers. The platform specific IPs will include the following key circuit technologies :
1) General purpose digital cells for logic (standard cell and gate array cell) in BiCMOS and CMOS processes. Libraries will consist of common primitives for logic implementation and include schematic, layout and Verilog models for simulations.
2) Analog Image Signal Processing (ISP) building IPs in Mixed Signal BiCMOS process: tape-out test chips to validate the functionalities and performance of these IPs. These circuits will be implemented in both 5V and 3.3V BiCMOS processes.
3) Develop 3.3 V-0.35u CMOS image signal processing AFE (Analog Front End) for colour CCD camera: include CMOS analog ISP building block IPs, high speed data converters ( ADC - Analog to Digital Converter and DAC - Digital to Analog Converter), tape-out and evaluate the AFE module to validate IPs functionalities and performance for commercial applications
MiniLogic Device Corporation
微創高科有限公司 [贊助機構]
本項目將研發專用集成電路設計平臺，主要用於混合信號CCD圖像傳感處理。該設計平臺以提高性能、降低成本、提升技術和實現商業化爲目標，適用於CCD圖像傳感處理、數據轉換、時序産生和CCD高壓時鐘驅動等周邊集成電路。主要的電路設計包括核心圖像信號處理IP、高速低功耗數據轉換器（ADC和DAC），標準數字邏輯單元、高精度振蕩器以及高電壓時鐘驅動器等，其芯片將用BiCMOS或CMOS工藝製成，可用於開發低成本低功耗高集成度的CCD圖像信號處理子系統（黑白或彩色）的解决方案。這一項目所開發的技術將不僅增强CCD圖像傳感處理電路的競爭力，其核心模擬IP還可以應用到CMOS圖像傳感處理電路中。