BLE SoC Architecture and System Design * RF transceiver architecture design for low cost, low power and high performance * Optimized digital baseband architecture for increased range and data throughput * System and modules specifications definition BLE Modules IP * Initial version RF transceiver IP design in terms of circuit schematic, netlist, simulation and layout * Initial version digital baseband IP in terms of algorithm, simulation platform and RTL code * Initial version analog and digital peripherals IP in terms of circuit schematic / RTL code, netlist, simulation and layout * Refined RF transceiver IP in terms of circuit schematic, netlist, simulation and layout * Refined digital baseband IP in terms of algorithm, simulation platform and RTL code * Refined analog and digital peripherals IP in terms of circuit schematic / RTL code, netlist, simulation and layout BLE SoC * Initial version of BLE 5 SoC engineering samples and evaluation boards * Refined version of BLE 5 SoC engineering samples and evaluation boards Reference Design * Reference design for the BLE 5 SoC
北京中电华大电子设计有限责任公司
东南大学
蓝牙5是蓝牙核心规格的重大更新，它为低功耗蓝牙的性功能和效益带来关键性提升。根据IndustryARC的市场研究，低功耗蓝牙设备的出货量可望於2020年达到84亿，年復合增长率达到29％。隨著覆盖范围，速度，以及广播信息容量上的提升，蓝牙5成为了理想的短距离无线技术，在物联网应用上开拓了新领域。本项目將会在射频收发器，数字基带以及其他知识產权的开发上採用创新关键技术，以达至目標性能。我们將会设计先进的射频收发器架构，其中包括直接调製发射器，低中频单转换接收器及优化数字基带，以达至理想的功率、成本和表现。至於新功能方面，2Mbps 物理层將会被开发以达到两倍数据速度的提升，而低功耗长距离则把有效通信距离增加四倍。在整个计划中，我们將透过两次流片去开发支援蓝牙5的低功耗蓝牙系统芯片，同时提供参考设计。此项目將提供支援蓝牙5標准的集成电路解决方案及知识產权產品组合。让我们的客户能藉著这更快速、更聪明和可靠的低功耗蓝牙技术，捕捉这快速增长的市场。