立體圖像信號處理器
ART/126CP
20120323 - 20140521
14765
李耀基先生
Algorithms Design
• Depth estimation & Video format conversion IPs and corresponding documentation
• Performance and simulation models for depth estimation & Video format conversion
Reference IC Implementation
• Frontend logical database(RTL) in Verilog format
• Physical layout in GDSII format
• Reference IC with processor core and peripherals
• Hardware spec, Implementation and verification documents
Development Platform
• FPGA development board for IP verification
• Reference IC test board and development platform
立體(三維)顯示近年在顯示技術的進步下逐漸流行。由於三維顯示內容需求日益增長,立體攝像機和類似的視頻採集設備將是下一代普及的消費電子產品。因此,集成電路產業需要建立高效率及成本效益的立體圖像信號處理器硬件,可以同時處理多個攝像機圖像視頻。該處理器的硬件可以產生多種格式輸出,以滿足視頻編碼器和三維顯示的各種要求。