高速捷變的直接數字綜合器

高速捷變的直接數字綜合器

  • 高速捷變的直接數字綜合器
    ART/140CP
    20121021 - 20150120
    12223

    嚴北平博士
    1) 1 GSPS (Sampling per second) DDS without internal clock (phase locked loop or PLL). All key blocks, including 32-bit DDS core, 12 bit high speed DAC, and efficient I/O interface, will be designed and verified based on CSMC 130 nm CMOS technology. 1 GSPS DDS samples without PLL will be delivered within the first 6 months. 2) 1 GSPS DDS with internal clock. A PLL circuit will be added in the above-mentioned 1GSPS DDS to facilitate the applications for clock source and siganl generation. 1 GSPS DDS IPs and samples with PLL will be delivered within 12 months. 1 GSPS DDS IPs include 1) 32-bit DDS core, 2) 12-bit high speed DAC, 3) efficient I/O and ESD interface, and 4) integrated 1 GSPS DDS. 3) 2 GSPS DDS without internal clock. All key blocks, including 32-bit DDS core, 12 bit high speed DAC, and high speed interface, will be designed and verified based on SMIC 65 nm technology. 2 GSPS DDS samples without PLL will be delivered within 15 months. 4) 2 GSPS DDS with internal clock. A PLL circuit will be added in the above-mentioned 2 GSPS DDS to facilitate the applications for clock source and siganl generation. 2 GSPS DDS IP and samples with PLL will be delivered within 21 months. 2 GSPS DDS IPs include 1) 32-bit DDS core, 2) 12-bit high speed DAC, 3) efficient I/O & ESD interface, and 4) integrated 2 GSPS DDS.
    王克中博士 鄺國權先生 霍曉博士 陳中子博士 蔡小五博士 Miss Sidar Lai Mr Norman FOK Mr Chenxi Wei Mr Tao Sun Miss Nan Guo Mr Leung Ling Alan Pun Mr Gangjie Jacky Cai Mr Tat Fu Chan Mr Zuqiang Tang Mr Sze Wing, Brian Leung Mr Zhuqing Joe Feng
    華潤上華科技有限公司 [贊助機構] 無錫華潤上華半導體有限公司(特許授權) [贊助機構] 中國科學院微電子研究所 興華半導體有限公司 興華半導體(合同服務) 中芯國際 [贊助機構] 中芯國際 (特許授權) [贊助機構]

    軟件無線電(SDR)是下一代無線通訊主要方向之一。它的基本思想就是利用軟件編程方法在單個收發硬件平臺上實現不同標準,不同模式的數據交換和通訊。因為要求收發機實現數字編程,所以直接數字頻率綜合器(DDS)成為SDR的關鍵部件之一。本項目的目標是利用ASTRI所提出的算法和電路架構,设计并驗證高速捷變的DDS芯片, 并將其IP授權與工業界使用。 所有設計將在EDA平臺上進行。利用特定Foundry提供的器件模型搭建DDS電路模塊,在電路設計和仿真完成後,進行版圖設計。完成版圖設計後,通過後仿真再次確認電路功能。經過DRC/LVS檢查無誤後,完成試驗芯片tape-out。實際電路功能驗證將在試驗芯片上測試和確認。 相對與傳統的頻率綜合器而言,DDS是一項新技術。由於DDS是所有數字通訊系統不可缺少的組成部份,它將為未來的SDR通訊技術帶來深遠的影響。本項目所開發的DDS還可用于許多其它領域﹐ 如自動測試設備(ATE)﹐ 醫學成像﹐電纜調制器﹐ 聲納浮標﹐ 和相控陣雷達系統。DDS 將會滲透到日常生活各個角落。