开发多媒体应用系统平台 (ART/009CP)

Combining Phase-1 and Phase-2:
25/11/2006 - 25/02/2007:
Completion of H.264 Main Profile and High Profile Algorithm & Architecture Design.
26/02/2007 - 25/08/2007:
Completion of Preliminary H.264 Main Profile and High Profile FPGA RTL Code.
25/11/2006 - 25/08/2007:
Completion of Emulation Platform Hardware Board
26/08/2007 – 25/11/2007:
Commitment of 10% contribution of the full project
26/08/2007 – 25/11/2007:
H.264 FPGA Module Level Integration and Testing
26/08/2007 – 24/02/2008:
Fine Tuning the H.264 FPGA in terms of performance and cost.
26/08/2007 – 25/01/2008:
Porting of Linux and drivers on the Emulation Platform
26/01/2008 – 24/02/2008:
Completion of Demo Software, Hardware, FPGA debugging, Conformance Testing and Performance Tuning.