On-chip ESD protection design for advanced silicon process

On-chip ESD protection design for advanced silicon process

  • Whole chip ESD protection scheme is designed to provide effective ESD protection for integrated circuits fabricated in several technology nodes. Protection devices are designed and verified using TCAD based process and device simulation, which are utilized in I/O ESD protection circuit and power clamps. Developed ESD protection schemes can provide effective ESD protection up to 8000V in Human Body Model (HBM) test without latch-up problem. Compact model for ESD protection devices is also provided to enable fast and efficient ESD simulation with core circuit.

    • Total ESD solutions for 0.5 um 200V SOI BCD process (HBM 2000V)
    • Total ESD solutions for 0.35um CMOS process (HBM 4000V)
    • Total ESD solutions for 0.13um CMOS process (HBM 2000V)
    • Total ESD solutions for 65nm CMOS process (HBM 2000V)
    • Total ESD solutions for 55nm CMOS process (HBM 8000V)
    • Total ESD solutions for 40nm CMOS process (HBM 2000V)
    • Total ESD solutions for 16nm CMOS process (HBM 2000V) (on-going)