SSD Controllor SoC with Super Speed USB3.0 (SCSU)

SSD Controllor SoC with Super Speed USB3.0 (SCSU)

  • SSD Controllor SoC with Super Speed USB3.0 (SCSU)
    ART/107CP
    20101115 - 20120815
    17032

    Mr Yiu-kei Li
    1. Silicon IP: USB3.0 device controller IP and SSD controller IP 2. The test vehicle: SSD controller SoC with USB3.0 interface 3. FPGA and evaluation platform: FPGA development board and demo firmware for IP verification; Evaluation board and firmware for USB3.0 SSD test vehicle.

    This project aims to develop Solid State Driver (SSD) controller SoC with super speed USB3.0 interface, which can support up to 5Gbps data rate. This project will implement the latest USB3.0 standard defined by USB Implements Forum (USB-IF) together with advance SSDcontroller to address the high performance portable mass-storage market needs. As the onward standard of USB2.0, the USB3.0 device should be capable to support the legacy USB2.0 device that has been largely deployed in current consumer and electronic market. By leveraging USB3.0 super speed, the SSD can achieve much higher bandwidth comparing to SATA2 and USB2.0. As a result, the USB3.0 SSD can easily penetrate both the traditional USB2.0 market and the emerging high performance mass-storage market like High Definition video real time storage market. As the following project of ITF High Performance Storage Controller (HPSC) full project, this new project will improve some modules which are developed by HPSC in order to fit for the new feature. This new project will also enhance concurrent bus architecture as well as the NAND Flash controller in order to support new synchronous NAND Flash standard like ONFi or Toggle mode. And the corresponding firmware will also be developed to maximize the data operation bandwidth and optimize the NAND Flash read/write efficiency. The error correction engine will also be re-designed to provide more robust capability to handle the higher bit error rate of MLC (multi level cell) NAND Flash. In addition to the enhancement of SSD controller, another complicated and valuable IP design will be the USB3.0 device controller which will be fully compliant to USB-IF USB3.0 standard. This IP will be integrated with SSD controller to be single test chip which will be taped out during this project. In the meantime, the USB3.0 device controller IP and SSD controller IP can be licensed independently to industrial. This project fits ASTRI’s technology roadmap to high performance controller and connectivity technology and provides industry with high performance and low cost solution through partnership and technology transfer. And this project is endorsed by local industry partners. This benefits ASTRI’s R&D to realize a high quality product with industry focus and it promotes technology transfer.