Mechanism-Based Software for 3D-Interconnect Fabrication
20130102 - 20140331:
Dr Xunqing Daniel Shi
1. The characterization methodology and database of basic electrochemical behavior of the 3 additives used in the Cu chemical solution, those would be delivered by one report. [Completion Date: 6 months after the project start] 2. The validated numerical models for modeling & simulating the electrochemical deposition (ECD) of the via filling process using the new additive interaction mechanism, those would be delivered by document and demonstration. [Completion Date: 6 months after the project start] 3. The numerical models for goodness quantification of 3D-interconnect in the ECD fabrication process using the boundary element technique, those would be delivered by document and demonstration. [Completion Date: 12 months after the project start] 4. The computational engine & recipe window optimization module for seamless via to wafer-level modeling and simulation of the via filling process, those would be delivered by document and demonstration. [Completion Date: 12 months after the project start] 5. The full version of the MS-3D software, including 4 key functional modules, i.e., the user interface, the ECD process modeling & simulation computational engine, the recipe window optimization and the result visualization with the recipe window tolerance less than 15%, which would be delivered by documentation and demonstration. [Completion Date: 15 months after the project start]
Dr Enboa Wu Ms YH KWAN Dr Ziyang GAO Dr Bin XIE Dr Yaofeng SUN Mr Yat Kit, Kolo TSUI Mr Andy LEE Mr Jackie CHAU Mr Carlos CHOW Mr WK LUK Mr Shu Kin YAU Dr Kwong Wa, Ken YEUNG Dr Yueping, Pearl YE Dr Peter WAN Dr Minghui GAO Mr Man Kai, Paul CHEUNG Dr Yan LIU Ms Karina KO Mr Jiye LUO Mr Hai XIA Mr Chen CHEN Mr Lourdito OLLERES Mr Jun CHEN Mr Xiangfeng SHAO Mr Delfin LAM Ms Juanna YAO Ms Fiona WANG Mr Ryan CHUNG Mr Jian, Rockey ZHU Mr Chee Kiong, Mike LOH Ms Zhen SU Mr Shaoqin XIE Mr Man Lung, Ivan SHAM Dr Song, Steve HE Dr Yuxing, Michael REN Dr Mingxiang XIAO Ms Wai Kee, Vicky LAI Ms Ya LV
China Wafer Level CSP Ltd. Hong Kong University of Science & Technology Huitai Digital Technology Holdings Limited [Sponsor] Huitai Digital Technology Holdings Limited (Technology Licensing) [Sponsor] Info Bright Technologies (H.K.) Co., Ltd. Shanghai Institute of Microsystem & Information Technology, China Shanghai Jiao Tong University, China Shanghai Sinyang Semiconductor Materials Co., Ltd.
3D-IC is expected to be widely applied in many electronics components, e.g., memory, CMOS image sensor (CIS), radio frequency integrated circuits (RFIC), micro-electro-mechanical-system (MEMS), etc. 3D-Interconnect is the sole solution today for 3D-stacking or integration of various ICs. 3D-Interconnect is fabricated by 4 major processes, i.e., via formation, via filling, wafer thinning and wafer stacking. Because the copper (Cu) via filling process is influenced by many parameters including geometry, electrochemistry and physics, it is very time-consuming and expensive for the industry to use the trial-and-error method to determine the optimal process recipe window. It becomes a major issue which hinders the wide applications of the 3D-IC packaging technology in different electronics products. In this project, an electrochemistry mechanism based software will be developed for modeling & simulating the electro-chemical deposition (ECD) of the Cu via filling process accurately and cost-effectively to determine the optimal recipe window for 3D-interconnect fabrication, and further shorten the time-to-market of 3D-IC based electronics products. First, based on the fundamental understanding of the electrochemical behavior (e.g., molecular size, transport rate, absorption rate, etc.) of the 3 additives (i.e., accelerator, suppressor, leveler) used in the Cu chemical solution, a new additive interaction mechanism, so-called competing & grouping mechanism, will be proposed to accurately describe the absorption and desorption of the 3 additives in the Cu via filling process. Many experiments will be conducted to validate the numerical models of the new mechanism. The software will embed the validated numerical models and includes four key modules, i.e., user interface, computational engine, optimal recipe window and result visualization. It will be developed as off-line and on-line tools for the user to determine the optimal process recipe window for 3D-interconnect fabrication in a quick and cost-effective manner. Based on the market research conducted by TechSearch, Prismark and Yole Development on applications of Cu pillar bumping, through-silicon-via (TSV) and Si interposer, the market size of the 3D-interconnect will be up to US$5.3B in 2015. The software to be developed in this project will not only enable the user to accurately and cost-effectively determine the optimal process recipe window for 3D-interconnect packaging fabrication and shorten the time-to-market of 3D-IC based electronics products, but more importantly, it will become a key tool for the industry to speed up the applications of 3D-IC technology to different electronics products to enter the 3D-IC era. As a result, it will definitely make ASTRI as one of the leaders in the 3D-IC packaging field in the world and enhance competitiveness of local companies and further increase their market share.