Feasibility study of a DDR4 analog PHY’s architectural design with industry standard DFI bus interface

Feasibility study of a DDR4 analog PHY’s architectural design with industry standard DFI bus interface

  • Feasibility study of a DDR4 analog PHY’s architectural design with industry standard DFI bus interface
    ARD/120
    20130220 - 20130819
    1980

    Mr David Kwong
    Dr K C Wang Mr Simon Lee Mr Andy Wu Ms Jennifer Ho Mr Ka Hung Kwok Mr K C Au Mr K C Wan Ms Sidar Lai