ESD design and device modeling
ART/069CP
20090701 - 20110331
10400
Mr David Kwong
• A technical report to elaborate on the methodology for ESD simulation-design, including simulation strategy, algorithm, simulation method and calibration techniques.
• ESD protection hard IPs (structure and layout) for the specific process technologies (CSMC’s 200 V SOI and 0.35 um logic process )
• Compact models based on new protection structure developed from this technology
CSMC Technologies Fab 2 Co Limited [Sponsor]
RCL Semiconductors Limited [Sponsor]
ESD (Electro Static Discharge) has become one of the most important reliability problems in IC industry. On-chip protection circuits are the only way to protect ICs from ESD. Currently, dominant ESD design methodology is a trial and error method, which is time consuming and not be able to reach the best protection structure. Therefore, the development of better ESD design methodology is not only a technical requirement, but also a market need. This project is going to develop simulation-design methodology that can give total solutions in ESD design, including 1) prediction capability 2) optimization capability and 3) design capability. The design-of-experiments modeling approach is presented as the basis of a complete IC ESD design methodology. The methodology will employ Synopsys TCAD as simulation tool, to use empirical modeling to predict the I-V snapback characteristics and ESD withstand level of a circuit given the circuit’s layout parameters. Moreover, circuit-level ESD modeling technique will be also developed to meet mixed mode simulation. The development of ESD simulation-design capability will fill in the technology gap in ESD design. The methodology will provide significant technical drive in IC ESD protection.