Configurable Multi-Standard Video Encoder with Embedded DSP Core and Hardware Accelerators (ENC-CMSD)

Configurable Multi-Standard Video Encoder with Embedded DSP Core and Hardware Accelerators (ENC-CMSD)

  • Configurable Multi-Standard Video Encoder with Embedded DSP Core and Hardware Accelerators (ENC-CMSD)
    ART/056CP
    20090201 - 20100531
    12500

    Dr Shen-chang Chao
    1. Configurable multi-standard AVS (AVS 1.0 and AVS-S) video encoder system design a. Programmable DSP-based architecture design with optimization in software & hardware partitioning DSP-based software + RTL code in FPGA) b. AVS 1.0 Profile high definition video encoder c. AVS-S video encoder 2. Fully verified RTL code in FPGA on a high performance DSP-based FPGA Emulation Platform for customer testing and integration. 3. One patent related to architecture and RTL code implementation 4. A report on the open-source multiple DSP encoder architecture designs with performance analysis comparing to the Tensilica solution. The report will include: 1) Analyze and select the most cost effective open-source DSP for this study. 2) Investigate the partition of the encoder codebase for multiple DSPs in order to achieve concurrency. 3) System Block Diagram of an open-source architecture that can achieve similar performance. 4) Performance comparison of the proposed open-source architecture with the Tensilica design in terms of system clock cycles, data through-put and latency. 5) Analysis of the encoder code-base using this open-source architecture (including DSP simulator) to get an estimated performance for comparison. 6) Trade-offs between these architectures.

    A configurable and software-programmable architecture based on a specific digital signal processor (Tensilica DSP) is proposed for this project. DSP is widely used for digital audio and video applications due to its outstanding computing performance, flexibility and configurability. Typically it requires 40-50% as many cycles as a general-purpose processor core to run a codec (encoders or decoders). The architecture will be optimized to achieve the requirement of real-time video processing with hardware accelerators approach. The objective of this full project is to develop configurable multi-standard AVS video encoders including AVS 1.0 and AVS-S with embedded DSP core and hardware accelerators design approach. In addition, a high performance and configurable DSP core-based FPGA development platform will be purchased in order to verify the design and to deliver FPGA-proven IP. ASTRI will collaborate with Hong Kong Universities (continuation of the previous video research projects) to develop the configurable multi-standard video encoding architecture with DSP core-based hardware implementation.