AVS FPGA Video/Audio Decoder on Emulation Platform
ART/022CP
20071001 - 20081231
14879
Dr Shen-chang Chao
1. MMP-AVS system design
a. AVS 1.0 and X-Profile architecture design
b. AVS 1.0 and X-Profile video decoder in FPGA
c. AVS audio decoder running on ARM processor
d. Fully verified RTL code in FPGA on the emulation board for customer testing and integration
e. Test vectors for standard conformance and quality and feature verification
f. Reference golden model for simulation and integration
g. Performance model for further optimization
2. Application software ready for future integration, OS, and drivers
3. Patents related to architecture and implementation
Beijing Bewinner Communications Company Limited
Hisense Hiview Tech Company Limited
ROXUS Technologies (China) Limited
TCL Corporate Research
The China's Audio Video Coding Standard (AVS) standard is a new initiative driven by consortia of Chinese device and system companies in defining a new generation of digital audio and video codec standards to meet the requirements of the digital audio and video industry and related technology development. The AVS Working Group was established with the approval of the Science and Technology Department of the China Ministry of Information Industry (MII) in June 2002. The AVS Working Group takes the responsibility for the formulation of technical standards related to equipment for multimedia compression, decompression, processing and presentation and products like digital audio and video systems. The initiatives for digital TV with AVS adoption is around the corner especially a strong driving force of a launch of High Definition Television broadcasting of 2008 Olympic Games in Beijing. China digital TV market has a long way from achieving analog switch-ff, which should enable huge growth opportunities in the digital TV sets, mobile TV and digital set top boxes markets for many years ahead. This Project is to develop the latest AVS audio and video decoding FPGA IP solutions including the latest standard, AVS X-Profile under Enterprise and Consumer Electronics (ECE) Group in ASTRI. The deliverables of this project include a complete set of advanced technology research, algorithm and architecture development, software models in different levels (C Model, Golden Model and Performance Model), hardware RTL code on FPGA format, test vectors for standard conformance and quality and feature verification, operating system and drivers on the emulation platform with application software ready for future integration that has been developed in other KTIs under ECE Group.