3D Wafer-Level Packaging (3D-WLP) Technologies for Low-Cost CMOS Image Sensor (CIS)
ART/104CP
20101201 - 20121130
17540
Dr Enboa Wu
By the end of this full project, the following documents/process recipes/product prototypes will be delivered:
- A polymer-based via-isolation manufacturing process including via formation, via isolation and via filling for TSV-based applications;
- Technical reports on TSV-based CIS products, including development trends, market status and potential applications;
- A low-resolution (e.g., VGA with 0.3Mp) CIS product prototype with at least 20% cost reduction vs. the state-of-art design using TSV-based 3D packaging technologies;
- At least 4 patents filed;
- A high-resolution (e.g., 5Mp) CIS product prototype with at least 20% cost reduction vs. the state-of-art design using TSV-based 3D packaging technologies.
Moore's Law has driven the semiconductor industry for more than 40 years. Recently, the Law has been found to encounter increasing great technological challenges in developing small feature size manufacturing technology and integrating different functional ICs in order to develop new electronic products with smaller form-factor, more functionalities and better long-term reliability. 3D packaging is a key technology that is proposed recently to address the above issues. In this project, the 3D wafer-level packaging (3D-WLP) technologies including design, process and testing will be developed. Furthermore, the technology platform will be applied to develop low-cost CMOS image sensor (CIS). As a result, two types of low-cost CIS prototype product, i.e., one with low resolution and the other with high resolution, will be developed. The success of this project will not only promote Hong Kong and China’s microelectronics packaging industry to the world-class level by establishing 3D-WLP capabilities but also enhance the industry’s competitiveness through developing high-performance and low-cost electronic products.