Topic: High Level Synthesis
Background Requirement for Workshop 4
As this is a hands-on workshop in advanced VLSI design with limited quota, priority will be given to participants with the following background:
1) VLSI design experience (ASIC of FPGA)
2) RTL (VHDL or Verilog) knowledge
3) ANSI-C or C++ knowledge is desirable, but not necessary
If you are interested in the event, please register at http://eie.polyu.edu.hk/event/ITS/ and indicate your job nature and/or background knowledge in the online registration form by 25 November 2015.
About ITS Workshop
Jointly organized by the Department of Electronic and Information Engineering, The Hong Kong Polytechnic University (PolyU EIE), Hong Kong Applied Science and Technology Research Institute (ASTRI), and Hong Kong Science and Technology Park (HKSTP), the Innovative Technology Series (ITS) seeks to keep the industry and the community abreast of the current and emerging technologies in electronic and information engineering. The ITS will be delivered in a series of 12 structural professional training workshops covering different topics of current and upcoming technologies as well as the latest research results. Presenters of the training workshops will be the professors of PolyU EIE and research project leaders of ASTRI. Overseas experts may also join the training workshops to share their experience with local industry and community.
|Venue||Room CF504, Department of Electronic and Information Engineering, The Hong Kong Polytechnic University, Hung Hom, Hong Kong|