FPGA Development
Associate Principal Engineer/Senior Lead Engineer/Lead Engineer/Engineer

Job Description


The Hong Kong Applied Science and Technology Research Institute (ASTRI) was founded by the Government of the Hong Kong Special Administrative Region in 2000 with the mission of enhancing Hong Kong’s competitiveness through applied research. ASTRI’s core R&D competence in various areas is grouped under five Technology Divisions: AI and Big Data Analytics; Communications; Cybersecurity, Cryptography and Trusted Technologies; Integrated Circuits and Systems; and IoT and Sensors. It is applied across five core areas which are Smart City, Financial Technologies, Intelligent Manufacturing, Digital Health, and Application Specific Integrated Circuits.

Over the years, ASTRI has nurtured a pool of research, I&T talents and received numerous international awards for its pioneering innovations as well as outstanding business and community contributions. To date, ASTRI has transferred over 800 technologies to the industries and been granted more than 900 patents in the Mainland, the US, and other countries.

To support our constant endeavour to position Hong Kong as a world-class smart city and an international hub of innovation and technology, we are seeking qualified professionals to fill the following position(s):

Job Responsibilities

  • Develop baseband solutions for 5G base stations and perform RTL coding in FPGA for 5G/6G PHY layer
  • Perform synthesis, Implementation, and speed & area optimization in FPGA
  • Design test bench and conduct simulations & debugging
  • Co-work with hardware and software Engineer in development


  • PhD holder, Master’s or Bachler’s in Computer Science, Computer Engineering, Electrical Engineering, Electronic Engineering, Information Engineering, Telecommunications, or relevant disciplines
  • Fresh graduates may also be considered as Engineer
  • Knowledge of wireless communication system, such as 3G/4G/5G, WiFi, Bluetooth, ZigBee a plus
  • Experience with Verilog RTL coding and testbench design
  • Familiar with large FPGA development on Xilinx devices
  • Experience with Xilinx’s build flow including design entry in Verilog, synthesis, place and route, timing constraints and timing closure
  • Experience with scripting languages: Python, tcl or equivalent, a plus
  • Lives ASTRI values


The appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work a five-day week.

For Application, please email [email protected] quoting the Ref. No. with an updated detailed resume. You are suggested NOT to include sensitive personal information such as HKID or passport number, photo, etc.

Position offer is subject to the applicant’s experience and academic qualification. The application will be open until the position is filled. Only short-listed candidates will be notified. ASTRI reserves the right not to fill the position.

ASTRI is an Equal Opportunities Employer. Personal data provided by job applicants will be used exclusively for recruitment only. For details, please refer to ASTRI Privacy Policy Statement., (https://www.astri.org/privacy/) in particular section 9.