Senior Lead Engineer/ Lead Engineer, ASIC Design
Careers

Senior Lead Engineer/ Lead Engineer, ASIC Design

Job Description

CTO/CCT/SSP/2721/210413
2021-04-13

Job Responsibilities

  • Assist in R&D project development
  • Conduct research in RISC-V architecture and Trusted Execution Environment
  • Carry out logic design, module-level or top-level verification
  • Work with the technical team to implement RISC-V SoC on FPGA
  • Carry out firmware design to support ASIC/FPGA development
  • Work with Software engineers to boot up RISC-V processor

Requirements

  • PhD holder or Master’s degree in Computer Engineering/ Electronic Engineering/ Electrical Engineering/ Information Engineering/ IC Design or relevant disciplines with minimum 3 years of related experience. Candidates with less experience may also be considered
  • Experience in HDL coding is a plus
  • Hands-on experience in IC design and verification is highly preferred
  • Experience in processor integration and development is an advantage
  • Knowledge on Trusted Execution Environment is an advantage
  • Experience in FPGA prototyping and debugging is an advantage
  • Live ASTRI values

Application

The appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work a five-day week.

Interested candidates, please send an application (quoting Ref. No.) with a detailed resume, current and expected salary to Talent Acquisition via email to [email protected]

The application will be open until the position is filled. Only short-listed candidates will be notified. ASTRI reserves the right not to fill the position.

ASTRI is an Equal Opportunities Employer. Personal data provided by job applicants will be used exclusively for recruitment only.