Senior Engineer (PI), FPGA Design

Job Description


Job Responsibilities

  • Assist in ITF R&D project as assigned;
  • Carry out micro-architecture design, RTL coding, FPGA prototyping and implementation;
  • Carry out algorithm optimization for hardware implementation;
  • Carry out module-level or top-level verification.


  • PhD degree holder in Computer Science, Electronic Engineering, Information Engineering or related area, including non-local applicant;
  • Hands-on experience in micro-architecture, RTL coding, FPGA prototyping and FPGA implementation;
  • Solid knowledge on computer architecture and micro-processor;
  • Familiar with FPGA/SoC design methodology and latest EDA tools;
  • Matlab/C, Perl, Cshell and Unix / Linux skills are preferred.
  • Knowledge on computer vision and machine learning is a plus.


Please send your application to [email protected] with your resume (word format) with attaching the PhD certificate / supporting document from the University; you must quote the Job Ref No. and include the following information:

  1. Name of University
  2. PhD obtained/expecting and when
  3. Have you participated in ITF Project Internship Program before? Yes/No
  4. If you answer Yes in item 3, please state the period
  5. Have you been employed by ASTRI before? If yes, please state the period
  6. Academic referee
  7. Your R&D skills
  8. Your work experience, if applicable

Application Deadline: until this position is filled. Only short-listed candidates will be notified.

ASTRI is an Equal Opportunities Employer.  Personal data provided by applicants will be used for consideration of an application only.  ASTRI reserves the right not to fill the position.