Senior Engineer (PI) / Engineer (PI), Digital IC Design

Job Description


The Hong Kong Applied Science and Technology Research Institute (ASTRI) was founded by the Government of the Hong Kong Special Administrative Region in 2000 with the mission of enhancing Hong Kong’s competitiveness through applied research. ASTRI’s core R&D competence in various areas is grouped under five Technology Divisions: AI and Big Data Analytics; Communications; Cybersecurity, Cryptography and Trusted Technologies; Integrated Circuits and Systems; and IoT and Sensors. It is applied across five core areas which are Smart City, Financial Technologies, Intelligent Manufacturing, Digital Health, and Application Specific Integrated Circuits.

Over the years, ASTRI has nurtured a pool of research, I&T talents and received numerous international awards for its pioneering innovations as well as outstanding business and community contributions. To date, ASTRI has transferred over 800 technologies to the industries and been granted more than 900 patents in the Mainland, the US, and other countries.

To support our constant endeavour to position Hong Kong as a world-class smart city and an international hub of innovation and technology, we are seeking qualified professionals to fill the following position(s):

Job Responsibilities

  • Participate in system design and develop system level model for digital and mixed signal simulation
  • Design, Implement, enhance and maintain RTL and verification code along with synthesis, DFT and Static Timing scripts for complex digital integrated circuits at the block, subsystem and system level
  • Generate supporting documentation for the digital IP design, implementation and verification
  • Document the design and simulation results for design reviews


  • Graduate in STEM-related discipline in Electronic Engineering or relevant discipline
  • A master’s degree or a doctoral degree’s holder is welcome to apply
  • Background in Digital IC design with experience in RTL development, verification and synthesis
  • Solid understanding of Verilog languages
  • Experience with Cadence design tools including NC Verilog, RTL Compiler and ENCOUNTER is preferred
  • Familiarity with MATLAB, C programming and TCL scripts is highly desirable


To apply, please email [email protected] with your resume. You are suggested NOT to include sensitive personal information such as HKID or passport number, photo, etc. 

Please quote the Job Ref No. and include the following information:

  1. Name of University
  2. Degree/PhD obtained/expecting and when
  3. Have you participated in ITF Research Talent Hub before? Yes/No
  4. If you answer Yes in item 3, please state the period
  5. Have you been employed by ASTRI before? If yes, please state the period

The application will be open until the position is filled while ASTRI reserves the right not to fill the position. Only short-listed candidates will be notified.

ASTRI is an Equal Opportunities Employer. Personal data provided by job applicants will be used exclusively for recruitment only. For details, please refer to ASTRI Privacy Policy Statement., in particular section 9.