- Responsible for schematics and layout design of mixed signal IC building blocks, including all facets of design flow, from schematics to layout, from initial floor-planning to final verification
- Develop new building blocks to cater for the requirements for speed and power consumption
- Develop new design technique and solutions for low power and high speed applications
- Work with team members and possess the ability to work closely with management team to meet or exceed design schedules
- Bachelor’s degree with 6+ year relevant experience, Master’s degree with 3+ year relevant experience or Ph.D in Electronic Engineering or related disciplines. Candidates with less experience will be considered as an Engineer
- Extensive experiences in mixed signal IC design, strong background in SRAM or memory compiler design will be a plus
- Familiar with Cadence/Mentor/Synopsys EDA tools; strong capability in programming using language such as Verilog, Skill, or TCL (Tool Command Language)
- Good experiences in ESD, IO or standard cell library design
- Good communication and interpersonal skills, a good team work player
Appointment will be on renewable contract terms with a competitive salary and performance-linked variable pay. Fringe benefits include paid leave, medical and dental benefits, insurance coverage and contribution to MPF. The incumbent will normally work under a five-day week schedule.
Interested candidates should send application (quoting Ref. No.) with detailed resume and, current and expected salary to the HR Department by email (preferable) or post no later than : 15 December 2017
Email: [email protected]
Post: 5/F, Photonics Centre, 2 Science Park East Avenue,
Hong Kong Science Park, Shatin, Hong Kong.
Only short-listed candidates will be notified. Personal data provided by applicants will be used for recruitment purposes only.
Late applications will not be considered.