- Responsible for layout designing and verification of SRAM memory compilers
- Develop layout coding skills and place & routing combining algorithm. Learn and apply these skills in memory compilers having transistor level layout design on advanced technologies
- Maintain accurate and complete documentation of work
- Graduate with a first-degree or higher degree in Electrical and Electronic Engineering or Computer Science, including non-local students, from a local university in Hong Kong.
- Successfully completed the undergraduate/postgraduate program
- Strong CMOS circuit fundamentals, in both digital and analog
- Hands-on experience with EDA tools such as Design Compiler, Physical Compiler, Spectre, HSPICE, etc.
- Knowledge of CMOS process and devices
- Experience working with place & route chip design tools
- Programming or scripting experience using TCL/Python/Skill
To apply, please email [email protected] with your resume, you must quote the Job Ref No. and include the following information:
1. Name of University
2. Degree obtained/expecting and when
3. Have you participated in ITF Project Internship Program before? Yes/No
4. If you answer Yes in item 3, please state the period
5. Have you been employed by ASTRI before? If yes, please state the period
6. Academic referee
7. Your R&D skills
8. Your work experience, if applicable
Application Deadline: 15 June 2017
Late applications will not be considered.