- Participate in system design and develop system level model for digital and mixed signal simulation;
- Design, Implement, enhance and maintain RTL and verification code along with synthesis, DFT and Static Timing scripts for complex digital integrated circuits at the block, subsystem and system level;
- Generate supporting documentation for the digital IP design, implementation and verification;
- Document the design and simulation results for design reviews.
- Graduate with a Bachelor or Master’s degree in Electronic Engineering or relevant disciplines, including non-local students, from a local university in Hong Kong.
- Successfully completed the undergraduate/postgraduate program.
- Background in Digital IC design with experience in RTL development, verification and synthesis.
- Solid understanding of Verilog languages.
- Experience with Cadence design tools including NC Verilog, RTL Compiler and ENCOUNTER is preferred.
- Familiarity with MATLAB, C programming and TCL scripts is highly desirable.
To apply, please email [email protected] with your resume, you must quote the Job Ref and include the following information:
- Name of the University
- Degree obtained/expecting and when
- Have you participated in the ITF Project Internship Program before? Yes/No
- If you answer Yes in item 3, please state the period
- Have you been employed by ASTRI before? If yes, please state the period
- Academic referee
- Your R&D skills
- Your work experience, if applicable
Application Deadline: until this position is filled. Only short-listed candidates will be notified.
ASTRI is an Equal Opportunities Employer. Personal data provided by applicants will be used for consideration of an application only. ASTRI reserves the right not to fill the position.