Low-power System-on-Chip (SoC) Design Platform
Power is a primary consideration in many segments of today’s electronics business. The thriving market for wireless/mobile devices such as cellphones, laptop and netbook, and home entertainment electronics such as set-top boxes, digital cameras and broadband modems, is driving the need for low-power and energy-efficient system-on-chip (SoC) designs.
Power consumption in chips, especially for technology at 90nm or below, must be lowered in order to reduce the packaging, reliability, manufacturing and operational costs of these devices. In addition, energy consumption as well as the amount of power loss over time, must be managed to extend the use time of battery-powered applications.
ICD has established a platform to provide a low-power solution for SoC design. The solution provides low-power management and implementation methods covering system level design, architecture definition, logic synthesis, physical implementation and final manufacturing.
There are two major sources of power consumption in an integrated chip (IC): leakage and dynamic. Key technologies developed in the platform mainly address the optimizations of leakage power and dynamic power consumption across a wide range of IC technologies.
- Leakage power optimization
- Multiple threshold voltage (Multi-Vth) CMOS cells
- Power gating
- Body biasing;
- Dynamic power optimization
- Clock gating
- Operand isolation
- Gate-level optimization
- Power-aware clock tree
- Multiple supply voltages.
With this comprehensive platform, the risk in developing low power SoC can be greatly reduced. Also, it can increase design efficiency and satisfy short time-to-market requirement.
Proportion of leakage power vs dynamic power on different process technologies
Power management strategy at different design levels
Low power SoC IC implementation methodology